There are three types of pulse width modulation: leading edge modulation (LEM), trailing edge modulation (TEM), and dual edge modulation (DEM). Typically LEM can be produced with one ramp, two comparators and a reference voltage which fixes the trailing edge of the pulse. TEM is accomplished by a similar arrangement but the reference voltage is at the beginning of the ramp to fix the leading edge of the pulse. These circuits produce but one pulse during every other clock cycle. As the ramp recovers, half of the clock cycle is unusable. In high speed applications two such circuits are used to provide a ramp during each half clock cycle so a sequence of alternate pulses is provided. To generate DEM, two ramps and two reference voltages are used, and in high-speed applications, again, two such circuits are used to obtain a sequence of alternating pulses. In another approach a phase locked loop (PLL) is employed with a triangular (dual ramp) waveform to obtain center justified DEM. While this approach does eliminate some of the redundancy of the prior arrangements it introduces the extra expense and complexity associated with PLLs. In addition, PLLs do not lend themselves to easy transition between formats LEM, TEM, DEM. The output of the PLL at lock may not line up exactly with other formats and so an offset adjust must be added. These offset adjusts are not always well controlled and need to be compensated.